1. Field of the Invention
The present invention relates to semiconductor memory device, and more particularly to an internal clock generating circuit in a synchronous type semiconductor memory device that generates an internal clock signal by synchronizing with an external clock signal applied from outside.
2. Brief Description of the Prior Art
In recent years, a microprocessor performs operations at high speed, for instance, from 100 MHz to hundreds of MHz. Dynamic semiconductor memory devices for main computer memories and the like, and static semiconductor memory devices for cache memories have been developed, to increase storage capacity and improve operational speed in response to users' demands. However, the operational speed of the semiconductor memory devices can not keep up with that of microprocessors. As a result, the microprocessor has to be held back at its stand-by state, while the semiconductor memory device performs an access operation to collect necessary data. As a result, the operational speed of the relatively slow processing semiconductor memory device determines the performance of an entire system to which the device is applied, and hampers efforts for improving the performance of the system.
In order to improve the performance of the system by reducing the difference in operational speed between the semiconductor memory device and the microprocessor, a synchronous type semiconductor memory device has been used for inputting and outputting data, by synchronizing with an external clock signal applied from outside. The synchronous type semiconductor memory device receives control signals, such as commands applied from outside by synchronizing with the external clock signal, and performs internal operations for inputting and outputting data by synchronizing with the clock signal. The data is inputted in response to the external clock signal, thereby enabling to transmit data at a high speed. Furthermore, since the control signals applied from outside are received by synchronizing with the clock signal, a timing to start internal operations can be determined by only an edge of the clock signal, without considering a margin caused by a skew between signals applied from outside. As a result, it can be possible to make an accessing operation at high speed.
For instance, a signal input system of a typical synchronous time semiconductor memory device such as a dynamic random access memory DRAM has been introduced in Japan Patent Application Laid Open No. 8-180677. In the aforementioned system, an internal signal is generated on basis of a reference clock signal applied from outside and a clock enable signal to enable or disable the reference clock signal. Operations of other circuits in the semiconductor memory device are synchronized with the internal clock signal and other clock signals relevantly generated by the internal clock signal.
On the other hand, Japanese Patent Application Laid Open No. 8-17182 has disclosed a method of generating internal command signals to determine internal operations of the memory by processing command signals applied from outside. However, the circuits of the aforementioned synchronous type semiconductor memory device can not latch external command signals until an internal clock signal is generated. In this regard, all operations after decoding commands are affected by the time lag generated in the internal clock generating circuit. In consequence, the access speed of the synchronous type semiconductor memory device may drop.
As described above, in the conventional synchronous type semiconductor memory device which receives command signals by synchronizing with an external clock signal applied from outside and performs internal operations to input and output data by synchronizing with the external clock signal, the access speed thereof has not been satisfactory to users. This is because there has been a stand-by cycle between read and write operations, or between write and read operations.
There has been a demand for a synchronous type semiconductor memory device, which can perform operations at super high speed without the stand-by cycle. In response to such users' demand, there was made a memory in which an external clock signal applied through a clock input pin is controlled at every clock switching cycle by an external clock enable signal applied through a clock enable pin. In order to improve the access speed, such synchronous type of memory does not include a dummy cycle between read and write cycles.
Therefore, it has been named as "Notum-around type RAM (NtRAM) or "zero-bus turnaround type RAM(ZBtRAM)". In the synchronous type of memory in which a dummy cycle or a stand-by cycle, the clock enable operation is performed at every cycle as soon as the external clock shifts high from its low level with the clock enable signal being kept at its low level, and a clock disable operation is performed as soon as the external clock shifts from its low level to its high level with the clock enable signal being kept at its high level. If the external clock is controlled at its disable state by the level of the clock enable signal, the memory should generate an internal clock without a clock shifting interval. If the clock enable signal applied at the aforementioned clock controlling operations is not controlled again by the clock signal, there will be no further problem. However, if the clock enable signal is influenced by the clock signal on determining a margin between setup time and hold time in the chip, there can be a time lag in the internal clock to be generated. In other words, the external clock enable signal to determine enable or disable of the external clock is synchronously controlled by the external clock signal to determine the internal margin between setup time and hold time of the clock enable signal. Then the internal clock enable signal thus generated determines enable and disable of the external clock signal, thereby performing the operations to generate the internal clock. As a result, the time that the internal clock is generated will be delayed by the time lag before the actual operations are related thereto. As described above, the time lag that occurred at the time of generating the internal clock slows down the data access speed of the semiconductor memory device, to thereby lower the entire functional capacity of the device. Therefore, in the synchronous type semiconductor memory device which performs data access operations by receiving the clock signal and the clock enable signal applied from outside, there is a need for developing a technique of generating an internal clock at minimum time lag in response to the external clock signal applied from outside.